Technical Field
The present invention generally relates to formation of a vertical fin field effect transistor (vertical FinFET) having reduced vertical channel width variation, and more particularly to a method of fabricating a FinFET having a channel with straight sidewalls and facetted bottom source/drain.
Description of the Related Art
A Field Effect Transistor (FET) typically has a source, a channel, and a drain, where current flows from the source to the drain, and a gate that controls the flow of current through the channel. Field Effect Transistors (FETs) can have a variety of different structures, for example, FETs have been fabricated with the source, channel, and drain formed in the substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate), and FinFETs have been formed with the channel extending outward from the substrate, but where the current also flows horizontally from a source to a drain. The channel for the FinFET can be an upright slab of thin rectangular Si, commonly referred to as the fin with a gate on the fin, as compared to a MOSFET with a single gate parallel to the plane of the substrate. Depending on the doping of the source and drain, an n-FET or a p-FET may be formed.
Examples of FETs can include a metal-oxide-semiconductor field effect transistor (MOSFET) and an insulated-gate field-effect transistor (IGFET). Two FETs also may be coupled to form a complementary metal oxide semiconductor (CMOS), where a p-channel MOSFET and n-channel MOSFET are coupled together.
With ever decreasing device dimensions, forming the individual components and electrical contacts becomes more difficult. An approach is therefore needed that retains the positive aspects of traditional FET structures, while overcoming the scaling issues created by forming smaller device components.